Notes on finite state automata by Charles F. Miller III

By Charles F. Miller III

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By default, an unconnected input port is a floating port, and hence shows “z” during simulation. The logic following it will also propagate the “z”, until gated off by an AND gate. The following figure shows the in1 floating in lower instantiation. Since in1 was used as logic input to both the gates, and is no more driving both of them, the logic gets optimized and simplified into a simple wire connection between in2 and out2. This connection still maintains the AND’ing logic required between these two ports, as per its design.

6 Can I use a Verilog function to define the width of a multi-bit port, wire, or reg type? The width elements of ports, wire or reg declarations require a constant in both MSB and LSB. Before Verilog 2001, it is a syntax error to specify a function call to evaluate the value of these widths. For example, the following code is erroneous before Verilog 2001 version. In the above example, get_high and get_low are both function calls of evaluating a constant result for MSB and LSB respectively. However, Verilog-2001 allows the use of a function call to evaluate the MSB or LSB of a width declaration.

The call of the function my_func within the initial-begin-end does not require a destination, since the return has been voided. Some other intermediate variable like int_result declared in the above example at the scope of that module can still be modified within the voided function. SystemVerilog also allows functions with a return to be called as a task by casting the function call to void. 6 What are the rules governing usage of a Verilog function? The following rules govern the usage of a Verilog function construct: A function cannot advance simulation-time, using constructs like #, @.

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