Fine- and Coarse-Grain Reconfigurable Computing by K. Tatas, K. Siozios, D. Soudris (auth.), Stamatis

By K. Tatas, K. Siozios, D. Soudris (auth.), Stamatis Vassiliadis, Dimitrios Soudris (eds.)

Fine- and Coarse-Grain Reconfigurable Computing supplies the fundamental strategies and development blocks for the layout of excellent- (or FPGA) and Coarse-Grain Reconfigurable Architectures. Recently-developed built-in structure layout and software-supported layout movement of FPGA and coarse-grain reconfigurable structure also are defined.
Part I includes broad surveys of FPGA and Coarse-Grain Reconfigurable Architectures:
The FPGA know-how is outlined, together with structure, common sense block constitution, interconnect, and configuration tools and current fine-grain reconfigurable architectures emerged from either academia and undefined. also, the implementation thoughts and CAD instruments built to facilitate the implementation of a approach in reconfigurable via the and academia are provided.
In addition the beneficial properties, the benefits and obstacles of the coarse-grain reconfigurable platforms, the explicit matters that are meant to be addressed in the course of the layout part, in addition to consultant current coarse-grain reconfigurable platforms are explained.
In half II, case experiences, leading edge examine effects approximately reconfigurable architectures and layout frameworks from 3 tasks AMDREL, MOLEN and ADRES&DRESC, and, a brand new class in accordance with microcoded architectural standards are described.
Fine- and Coarse-Grain Reconfigurable Computing is a vital reference for researchers and pros and will be used as a textbook by means of undergraduate, graduate scholars and professors.
Foreword via Yale Patt, Jim Smith and Mateo Valero

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Virtex-4 devices are produced on a 90 nm copper process, using 300 mm (12 inch) wafer technology. Configurable Logic Blocks (CLBs) A CLB resource is made up of four slices. Each slice is equivalent and contains: • • • • • • Two function generators (F & G) Two storage elements Arithmetic logic gates Large multiplexers Fast carry look-ahead chain Horizontal cascade chain The function generators F & G are configurable as 4-input look-up tables (LUTs). Two slices in a CLB can have their LUTs configured as 16-bit shift registers, or as 16-bit distributed RAM.

6 LP_PGA II The LP_PGA II [36], is a stand-alone FPGA of 256 logic blocks with an equivalent logic capacity of 512 4-input LUTs. At this paragraph the implementation is described at the different components of the FPGA (logic block, connection boxes, interconnect levels, and the configuration architecture). 25 μm CMOS process from STMicroelectronics. Configurable Logic Block The LP_PGA II CLB is illustrated in Fig. 14. It is implemented as a cluster of 3-input LUTs. This clustering technique makes it possible to combine the results of the four 3-input LUTs in various ways to simultaneously realize up to three different functions in a logic block.

A single LE also supports dynamic single bit addition or subtraction mode selectable by an LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and direct link interconnects. The Stratix logic element schematic is shown in Fig. 22. Each LE has three outputs that drive the local, row, and column routing resources. The LUT or register output can drive these three outputs independently. Two LE outputs drive column or row and direct link routing connections and one drives local interconnect resources.

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