By Himanshu Bhatnagar
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® describes the complex innovations and strategies used for ASIC chip synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. moreover, the complete ASIC layout circulate method exact for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this publication is on real-time program of Synopsys instruments used to strive against a variety of difficulties visible at VDSM geometries. Readers should be uncovered to an efficient layout method for dealing with advanced, sub-micron ASIC designs. importance is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT test insertion, hyperlinks to structure, and static timing research. At each one step, difficulties on the topic of each one part of the layout circulate are pointed out, with ideas and work-arounds defined intimately. furthermore, the most important concerns regarding structure, which include clock tree synthesis and back-end integration (links to format) also are mentioned at size. moreover, the publication includes in-depth discussions at the fundamentals of Synopsys expertise libraries and HDL coding kinds, precise in the direction of optimum synthesis strategies.
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® is meant for an individual who's serious about the ASIC layout method, ranging from RTL synthesis to ultimate tape-out. goal audiences for this e-book are practising ASIC layout engineers and graduate scholars project complicated classes in ASIC chip layout and DFT options.
From the Foreword:
`This publication, written by means of Himanshu Bhatnagar, presents a accomplished assessment of the ASIC layout circulate exact for VDSM applied sciences utilizing the Synopsis suite of instruments. It emphasizes the sensible concerns confronted by means of the semiconductor layout engineer when it comes to synthesis and the combination of front-end and back-end instruments. conventional layout methodologies are challenged and designated ideas are provided to aid outline the following iteration of ASIC layout flows. the writer offers various functional examples derived from real-world occasions that might end up useful to training ASIC layout engineers in addition to to scholars of complex VLSI classes in ASIC design'.
Dr Dwight W. Decker, Chairman and CEO, Conexant structures, Inc., (Formerly, Rockwell Semiconductor Systems), Newport seashore, CA, USA.
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This step reduces the synthesislayout iteration time, especially since cell placement and global routing may take much less time than detailed routing the entire chip. However, if the 31 TUTORIAL cells are placed optimally with minimal congestion, detailed routing is also very fast. In any case, extraction of delays after the global route phase (albeit estimates) provides a faster method of getting closer to the real delay values that are extracted from the layout database after the detailed routing phase.
The fixed transition value (again approximating the final clock tree number) of clock prevents PT from calculating incorrect delay values, that are based upon the slow input ramp to the flops. The script to perform the hold-time analysis at the pre-layout level is shown below . db library. 3 SDF Generation To perform timing simulation, you will need the SDF file for back annotation. The static timing was performed using PT; therefore it is prudent that the SDF file be generated from PT itself. However, most designers feel comfortable in using DC to generate the SDF file.
This is a layout dependent feature , therefore will not be discussed here. 5 Post-Layout Steps The post-layout steps involve, verifying the design for timing with actual delays back annotated; functional simulation of the design; and lastly, performing LVS and DRC . Let us presume that the design has been fully routed with minimal congestion and area . The finished layout surface must then be extracted to get the actual parasitic capacitances and interconnect RC delays. Depending upon the 36 Chapter 2 layout tool and the type of extraction, the extracted values are generally written out in the SDF format for the interconnect RC delays, while the parasitic information is generated as a string of set joad commands for each net in the design.