A Pipelined Multi-core MIPS Machine Hardware Implementation by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

This monograph is predicated at the 3rd author's lectures on machine structure, given in the summertime semester 2013 at Saarland collage, Germany. It encompasses a gate point development of a multi-core computer with pipelined MIPS processor cores and a sequentially constant shared memory.

The e-book includes the 1st correctness proofs for either the gate point implementation of a multi-core processor and likewise of a cache established sequentially constant shared reminiscence. This opens how one can the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and hence deterministic. by contrast the reference types opposed to which correctness is proven are nondeterministic. the improvement of the extra equipment for those proofs and the correctness facts of the shared reminiscence on the gate point are the most technical contributions of this work.

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Gates for n-bit wide inputs n=1: a0 n 2 n > 1 : a[n − 1 : ] a[ n 2 n 2 n 2 ◦ ◦ ◦ b − 1 : 0] b n Fig. 11. Implementation of an n-bit ◦-tree for ◦ ∈ {∧, ∨, ⊕} Recursive construction is shown in Fig. 11. The inputs a[n − 1 : 0] and outputs zero and nzero of an n-zero tester shown in Fig. 12 satisfy zero ≡ a = 0n nzero ≡ a = 0n . The implementation uses n−1 nzero(a[n − 1 : 0]) = ai i=0 , zero = nzero . 2 Some Basic Circuits a a n n ∨ n-Zero 1 zero 37 nzero 1 nzero zero (a) symbol (b) implementation Fig.

For inverters the argument is equally simple. For values t satisfying hold(y, t), we define lreg(y, t) as the last value t before t when signal propagation was regular: lreg(y, t) = max{t | t < t ∧ reg(y, t )} . Now we can complete the definition of the value of gate y at time t: ⎧ in1(y)(t) reg(y, t) ∧ y is an inverter ⎪ ⎪ ⎪ ⎨in1(y)(t) ◦ in2(y)(t) reg(y, t) ∧ y is a ◦-gate y(t) = ⎪ hold(y, t) ⎪ ⎪y(lreg(y, t)) ⎩ Ω otherwise . 3 Timing Analysis Timing analysis is performed in the detailed model in order to ensure that all register inputs x[i]in and clock enables x[i]ce are stable at clock edges.

An equation e = e is an identity iff for any substitution of the variables a = a[1 : n] ∈ Bn , expressions e and e evaluate to the same value in B: ∀a ∈ Bn : e(a) = e (a) . • Equations which one wants to solve. A substitution a = a[1 : n] ∈ Bn solves equation e = e if e(a) = e (a). We observe that identities and equations we want to solve do differ formally in the implicit quantification. , to be implicitly quantified over all free variables. 6 Boolean Algebra 23 side of an equation represents an entity being defined.

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